The invention pertains chiefly to the field of programmable integrated memories such as EEPROM or FLASH EEPROM type memories.
The memories of this type that are currently being developed take the form of integrated circuits containing a set of resources that enable the programming and, if necessary, the erasure of the memory cells. These resources are notably programming and erasure voltage generators, circuits for the checking of the programmed or erased data elements by re-reading or address generators used for the automatic erasure of the entire memory or of certain selected sectors. These resources are controlled by an integrated control unit capable of performing algorithms adapted to the operations to be carried out and to the resources controlled.
The control unit is a state machine that can be constituted by means of a programmable logic array (PLA) or a microprogrammed unit. For reasons of space requirements, the state machine is generally wired.
The consequence of this is that the algorithms that can be performed by the state machine cannot be modified after the manufacture of the integrated circuit.
The devising and perfecting of such products is made easy by simulation programs applicable to the technology used. However, these programs are not an exact reflection of reality and therefore do not make it possible to do without the real tests to which prototypes are subjected. Typically, these tests consist of performing a succession of programming and erasure operations followed by re-reading operations used to detect the discrepancies between the data elements that should have been written and the data elements read. These tests can also be carried out by subjecting the memory to extreme operating conditions, for example, by placing the memory in an oven.
These tests are aimed of course at detecting the origin of the defects observed in order to modify certain design or manufacturing parameters accordingly.
Thus, the presently used designing methods generally call for the manufacture of several series of prototypes incorporating successive improvements resulting from the analyses of the tests made.
The search for the causes of the defects observed is made possible by integrated test modes enabling notably the extraction, from the memory, of the indicators representing the logic state of the main circuits that constitute it. For certain types of defects, such as those related to manufacturing variations and ageing, improvements can be obtained simply by a modification of the algorithms that can be performed by the state machine. However, many prototypes may have to be manufactured in order to enable the necessary modifications to be determined in an optimum way. This results in an increase in the cost and time taken to develop such products.
The invention is aimed at overcoming this drawback by proposing a memory designed to operate in an emulation mode enabling a tester, external to the integrated circuit, to be substituted for the state machine. This arrangement will then make it possible to test new algorithms without its being necessary to manufacture corresponding prototypes.
To this end, an object of the invention is a programmable integrated circuit memory comprising:
a matrix of addressable memory cells, PA1 supply means designed for the selective application of the programming and erasure voltages to said memory cells as a function of internal control signals conveyed by internal control lines, PA1 an interface circuit connected to external data and address lines to exchange data elements and to transfer external address signals to corresponding internal lines, PA1 a user's control unit receiving external control signals and designed notably to control said exchange of data elements as a function of said external control signals, PA1 a state machine designed to perform at least one algorithm that can be activated by the user's control unit as a function of the external control signals received, the performance of said algorithm having the effect of producing output signals, wherein said memory comprises detection means sensitive to predetermined external control signals and first selection means controlled by said detection means to make the memory work selectively in a normal mode and an emulation mode and wherein said first selection means are designed, in normal mode, to place said output signals of the state machine on said internal control lines and, in emulation mode, to place a part at least of said internal address lines in a state of communication with said internal control lines.
Should the memory be provided with a sequencer and an integrated clock, it is generally necessary to synchronize the sequencing of the algorithm by means of one and the same clock signal as the one used to synchronize the sequencer. To this end, it is possible to provide for the possibility of extracting the basic clock signal from the integrated circuit in order to transmit it to the tester. However, in emulation mode, it is preferable to synchronize the memory by means of a clock signal given by the tester.
Thus, according to another aspect of the memory of the invention, there is provided a memory wherein said state machine comprises a sequencer synchronized by at least one basic clock signal and wherein second selection means controlled by said detection means are designed to deliver said basic clock signal or signals selectively by means of an internal clock in normal mode and on the basis of at least one of said internal address lines in emulation mode.
This approach has the advantage of simplifying the checking of the exchanges between the tester and the integrated circuit. Furthermore, it can be used to carry out tests by modifying the basic clock frequency.
Should the state machine be provided with input terminals designed to receive input signals from at least one of the circuits of the memory, the invention further provides for third selection means controlled by said detection means and designed, in emulation mode, to give said input signals to said interface circuit with a view to placing them on said external data lines.
Advantageously, the interface circuit and the first, second and third selection means are designed to enable real-time operation.
Should the state machine be designed to control a plurality of circuits of the memory, it is also provided, according to the invention, that the internal control lines will constitute a control bus and that at least a part of the control circuits will be provided with decoders connected to the bus so that the number of lines constituting the control bus is not greater than the number of internal address lines.
The latter arrangement also enables an implementation of the emulation mode without its being necessary to provide for additional external lines or to use the external data lines.